// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_iob_rx_odr_reg_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:00 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_IOB_RX_ODR_REG_C_UNION_DEFINE_H__
#define __HIPCIEC_AP_IOB_RX_ODR_REG_C_UNION_DEFINE_H__

/* Define the union U_IB_ORDER_QUEUE_MODE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_0                   : 30  ; /* [31:2] */
        unsigned int    cfg_ib_order_queue_mode : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ORDER_QUEUE_MODE;

/* Define the union U_IB_ORDER_PORT_MODE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_1                         : 16  ; /* [31:16] */
        unsigned int    cfg_ib_port_dispatch_to_queue : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ORDER_PORT_MODE;

/* Define the union U_IB_ODR_MODE_CFG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_2                : 24  ; /* [31:8] */
        unsigned int    cfg_odr_p_bresp_mode : 1  ; /* [7] */
        unsigned int    cfg_gen_cpl_mode     : 1  ; /* [6] */
        unsigned int    cfg_p_odr_mode       : 2  ; /* [5:4] */
        unsigned int    cfg_cpl_odr_mode     : 2  ; /* [3:2] */
        unsigned int    cfg_np_odr_mode      : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_MODE_CFG;

/* Define the union U_IB_ODR_ERR_INJECT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_3                                : 14  ; /* [31:18] */
        unsigned int    cfg_npq_sbm_resp_err_inject          : 1  ; /* [17] */
        unsigned int    cfg_npq_sbm_data_err_inject          : 1  ; /* [16] */
        unsigned int    cfg_npq_sbm_ecc_err_inject           : 2  ; /* [15:14] */
        unsigned int    cfg_pcpl_sbm_ecc_err_inject          : 2  ; /* [13:12] */
        unsigned int    cfg_np_hdr_addr_sram_ecc_err_inject  : 2  ; /* [11:10] */
        unsigned int    cfg_p_hdr_addr_sram_ecc_err_inject   : 2  ; /* [9:8] */
        unsigned int    cfg_sram_ecc_err_inject_reserved     : 2  ; /* [7:6] */
        unsigned int    cfg_np_hdr_attr_sram_ecc_err_inject  : 2  ; /* [5:4] */
        unsigned int    cfg_p_hdr_attr_sram_ecc_err_inject   : 2  ; /* [3:2] */
        unsigned int    cfg_cpl_hdr_attr_sram_ecc_err_inject : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_ERR_INJECT;

/* Define the union U_IB_ODR_NPQ_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_4                     : 26  ; /* [31:6] */
        unsigned int    cfg_npq_atomic_blk_mode   : 2  ; /* [5:4] */
        unsigned int    cfg_npq_sbm_port_arb_mode : 1  ; /* [3] */
        unsigned int    cfg_npq_resp_err_resp_ur  : 1  ; /* [2] */
        unsigned int    cfg_npq_tlb_abort_resp_ur : 1  ; /* [1] */
        unsigned int    cfg_gen_cpl_arb_mode      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_NPQ_CTRL;

/* Define the union U_IB_ODR_NPQ_BUF_THRES */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_npq_port14_buf_thres : 4  ; /* [31:28] */
        unsigned int    cfg_npq_port12_buf_thres : 4  ; /* [27:24] */
        unsigned int    cfg_npq_port10_buf_thres : 4  ; /* [23:20] */
        unsigned int    cfg_npq_port8_buf_thres  : 4  ; /* [19:16] */
        unsigned int    cfg_npq_port6_buf_thres  : 4  ; /* [15:12] */
        unsigned int    cfg_npq_port4_buf_thres  : 4  ; /* [11:8] */
        unsigned int    cfg_npq_port2_buf_thres  : 4  ; /* [7:4] */
        unsigned int    cfg_npq_port0_buf_thres  : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_NPQ_BUF_THRES;

/* Define the union U_IB_ODR_AER_RPT_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_5                : 31  ; /* [31:1] */
        unsigned int    cfg_aer_rpt_adv_post : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_AER_RPT_CTRL;

/* Define the union U_IB_ODR_PQ_MERGE_CFG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_6                         : 30  ; /* [31:2] */
        unsigned int    cfg_so_interlved_merge_enable : 1  ; /* [1] */
        unsigned int    cfg_pq_merge_enable           : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_PQ_MERGE_CFG;

/* Define the union U_IB_ODR_SO_CTRL_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_ib_odr_so_set_7 : 4  ; /* [31:28] */
        unsigned int    cfg_ib_odr_so_set_6 : 4  ; /* [27:24] */
        unsigned int    cfg_ib_odr_so_set_5 : 4  ; /* [23:20] */
        unsigned int    cfg_ib_odr_so_set_4 : 4  ; /* [19:16] */
        unsigned int    cfg_ib_odr_so_set_3 : 4  ; /* [15:12] */
        unsigned int    cfg_ib_odr_so_set_2 : 4  ; /* [11:8] */
        unsigned int    cfg_ib_odr_so_set_1 : 4  ; /* [7:4] */
        unsigned int    cfg_ib_odr_so_set_0 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SO_CTRL_0;

/* Define the union U_IB_ODR_SO_CTRL_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_7                       : 27  ; /* [31:5] */
        unsigned int    cfg_ib_odr_so_ostd_limit_en : 1  ; /* [4] */
        unsigned int    cfg_ib_odr_so_ostd_num      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SO_CTRL_1;

/* Define the union U_IB_ODR_SO_CTRL_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_ib_odr_hash_key_low : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SO_CTRL_2;

/* Define the union U_IB_ODR_SO_CTRL_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_8                    : 16  ; /* [31:16] */
        unsigned int    cfg_ib_odr_hash_key_high : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SO_CTRL_3;

/* Define the union U_IB_ODR_SO_CTRL_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_9                  : 24  ; /* [31:8] */
        unsigned int    cfg_ib_odr_so_set_mode : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SO_CTRL_4;

/* Define the union U_IB_ODR_THRESHOLD */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_10                          : 8  ; /* [31:24] */
        unsigned int    cfg_ib_odr_pq_block_threshold   : 8  ; /* [23:16] */
        unsigned int    cfg_ib_odr_cplq_block_threshold : 8  ; /* [15:8] */
        unsigned int    cfg_ib_odr_npq_block_threshold  : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_THRESHOLD;

/* Define the union U_IB_ODR_SBM_THRESHOLD */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_ib_odr_cpl_sbm_free_threshold    : 8  ; /* [31:24] */
        unsigned int    cfg_ib_odr_sbm_pfull_clear_threshold : 8  ; /* [23:16] */
        unsigned int    cfg_ib_odr_sbm_pfull_high_threshold  : 8  ; /* [15:8] */
        unsigned int    cfg_ib_odr_sbm_pfull_low_threshold   : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SBM_THRESHOLD;

/* Define the union U_IB_ODR_BW_CAL_EN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_11                  : 30  ; /* [31:2] */
        unsigned int    dfx_cplq_disp_bw_cal_en : 1  ; /* [1] */
        unsigned int    dfx_pq_disp_bw_cal_en   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_BW_CAL_EN;

/* Define the union U_IB_ODR_BW_CAL_CLR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_12                   : 30  ; /* [31:2] */
        unsigned int    dfx_cplq_disp_bw_cal_clr : 1  ; /* [1] */
        unsigned int    dfx_pq_disp_bw_cal_clr   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_BW_CAL_CLR;

/* Define the union U_IB_ODR_NPQ_SBM_STAT_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_13                        : 24  ; /* [31:8] */
        unsigned int    cfg_npq_gen_cpl_stat_port     : 4  ; /* [7:4] */
        unsigned int    rsv_14                        : 2  ; /* [3:2] */
        unsigned int    cfg_npq_gen_cpl_stat_port_sel : 1  ; /* [1] */
        unsigned int    cfg_npq_gen_cpl_stat_en       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_NPQ_SBM_STAT_CTRL;

/* Define the union U_IB_ODR_NPQ_SBM_GEN_CPL_MODE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_15                    : 31  ; /* [31:1] */
        unsigned int    cfg_npq_sbm_resp_err_mode : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_NPQ_SBM_GEN_CPL_MODE;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL_RD_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_16                   : 22  ; /* [31:10] */
        unsigned int    cfg_dfx_queue_tbl_rd_en  : 1  ; /* [9] */
        unsigned int    cfg_dfx_queue_tbl_rd_idx : 9  ; /* [8:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL_RD_REQ;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL_RD_VLD */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_17                   : 31  ; /* [31:1] */
        unsigned int    cfg_dfx_queue_tbl_rd_vld : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL_RD_VLD;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl_rd_data_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_0;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl_rd_data_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_1;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl_rd_data_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_2;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl_rd_data_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_3;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_REQ */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_18                 : 22  ; /* [31:10] */
        unsigned int    cfg_dfx_hdr_buf_rd_en  : 1  ; /* [9] */
        unsigned int    cfg_dfx_hdr_buf_rd_idx : 9  ; /* [8:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_REQ;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_VLD */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_19                 : 31  ; /* [31:1] */
        unsigned int    cfg_dfx_hdr_buf_rd_vld : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_VLD;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_DATA_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_hdr_buf_rd_data_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_DATA_0;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_DATA_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_hdr_buf_rd_data_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_DATA_1;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_DATA_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_hdr_buf_rd_data_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_DATA_2;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_DATA_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_hdr_buf_rd_data_3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_DATA_3;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_DATA_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_hdr_buf_rd_data_4 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_DATA_4;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_DATA_5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_hdr_buf_rd_data_5 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_DATA_5;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_DATA_6 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_hdr_buf_rd_data_6 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_DATA_6;

/* Define the union U_IB_ODR_DFX_HDR_BUF_RD_DATA_7 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_hdr_buf_rd_data_7 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_HDR_BUF_RD_DATA_7;

/* Define the union U_IB_ODR_DFX_QUEUE_TYPE_RO_SEL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_20                   : 30  ; /* [31:2] */
        unsigned int    cfg_dfx_queue_tbl_ro_sel : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TYPE_RO_SEL;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL0_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl0_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL0_RO_0;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL0_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl0_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL0_RO_1;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL1_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl1_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL1_RO_0;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL1_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl1_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL1_RO_1;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL2_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl2_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL2_RO_0;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL2_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl2_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL2_RO_1;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL3_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl3_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL3_RO_0;

/* Define the union U_IB_ODR_DFX_QUEUE_TBL3_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_tbl3_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_TBL3_RO_1;

/* Define the union U_IB_ODR_DFX_NP_HDR_BUF_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_np_hdr_buf_ro : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_NP_HDR_BUF_RO;

/* Define the union U_IB_ODR_DFX_P_HDR_BUF_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_p_hdr_buf_ro : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_P_HDR_BUF_RO;

/* Define the union U_IB_ODR_DFX_CPL_HDR_BUF_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_cpl_hdr_buf_ro : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPL_HDR_BUF_RO;

/* Define the union U_IB_ODR_DFX_PCPL_SBM_RO_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_pcpl_sbm_ro_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PCPL_SBM_RO_0;

/* Define the union U_IB_ODR_DFX_PCPL_SBM_RO_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_pcpl_sbm_ro_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PCPL_SBM_RO_1;

/* Define the union U_IB_ODR_DFX_PCPL_SEND_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_pcpl_send_ro : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PCPL_SEND_RO;

/* Define the union U_IB_ODR_DFX_QUEUE_DISP_RO */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_disp_ro : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_DISP_RO;

/* Define the union U_IB_ODR_PORT_IDLE_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_odr_port_idle_status : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_PORT_IDLE_STATUS;

/* Define the union U_IB_ODR_DFX_PQ_BW_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_disp_max_bw_0 : 16  ; /* [31:16] */
        unsigned int    dfx_pq_disp_ava_bw_0 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PQ_BW_0;

/* Define the union U_IB_ODR_DFX_PQ_BW_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_disp_max_bw_1 : 16  ; /* [31:16] */
        unsigned int    dfx_pq_disp_ava_bw_1 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PQ_BW_1;

/* Define the union U_IB_ODR_DFX_PQ_BW_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_disp_max_bw_2 : 16  ; /* [31:16] */
        unsigned int    dfx_pq_disp_ava_bw_2 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PQ_BW_2;

/* Define the union U_IB_ODR_DFX_PQ_BW_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_disp_max_bw_3 : 16  ; /* [31:16] */
        unsigned int    dfx_pq_disp_ava_bw_3 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PQ_BW_3;

/* Define the union U_IB_ODR_DFX_PQ_BW_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_disp_max_bw_4 : 16  ; /* [31:16] */
        unsigned int    dfx_pq_disp_ava_bw_4 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PQ_BW_4;

/* Define the union U_IB_ODR_DFX_PQ_BW_5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_disp_max_bw_5 : 16  ; /* [31:16] */
        unsigned int    dfx_pq_disp_ava_bw_5 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PQ_BW_5;

/* Define the union U_IB_ODR_DFX_PQ_BW_6 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_disp_max_bw_6 : 16  ; /* [31:16] */
        unsigned int    dfx_pq_disp_ava_bw_6 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PQ_BW_6;

/* Define the union U_IB_ODR_DFX_PQ_BW_7 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_pq_disp_max_bw_7 : 16  ; /* [31:16] */
        unsigned int    dfx_pq_disp_ava_bw_7 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PQ_BW_7;

/* Define the union U_IB_ODR_DFX_CPLQ_BW_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_cplq_disp_max_bw_0 : 16  ; /* [31:16] */
        unsigned int    dfx_cplq_disp_ava_bw_0 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPLQ_BW_0;

/* Define the union U_IB_ODR_DFX_CPLQ_BW_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_cplq_disp_max_bw_1 : 16  ; /* [31:16] */
        unsigned int    dfx_cplq_disp_ava_bw_1 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPLQ_BW_1;

/* Define the union U_IB_ODR_DFX_CPLQ_BW_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_cplq_disp_max_bw_2 : 16  ; /* [31:16] */
        unsigned int    dfx_cplq_disp_ava_bw_2 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPLQ_BW_2;

/* Define the union U_IB_ODR_DFX_CPLQ_BW_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_cplq_disp_max_bw_3 : 16  ; /* [31:16] */
        unsigned int    dfx_cplq_disp_ava_bw_3 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPLQ_BW_3;

/* Define the union U_IB_ODR_DFX_CPLQ_BW_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_cplq_disp_max_bw_4 : 16  ; /* [31:16] */
        unsigned int    dfx_cplq_disp_ava_bw_4 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPLQ_BW_4;

/* Define the union U_IB_ODR_DFX_CPLQ_BW_5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_cplq_disp_max_bw_5 : 16  ; /* [31:16] */
        unsigned int    dfx_cplq_disp_ava_bw_5 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPLQ_BW_5;

/* Define the union U_IB_ODR_DFX_CPLQ_BW_6 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_cplq_disp_max_bw_6 : 16  ; /* [31:16] */
        unsigned int    dfx_cplq_disp_ava_bw_6 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPLQ_BW_6;

/* Define the union U_IB_ODR_DFX_CPLQ_BW_7 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_cplq_disp_max_bw_7 : 16  ; /* [31:16] */
        unsigned int    dfx_cplq_disp_ava_bw_7 : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPLQ_BW_7;

/* Define the union U_IB_ODR_DFX_NP_HDR_BUF_RC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_np_hdr_buf_rc : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_NP_HDR_BUF_RC;

/* Define the union U_IB_ODR_DFX_P_HDR_BUF_RC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_p_hdr_buf_rc : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_P_HDR_BUF_RC;

/* Define the union U_IB_ODR_DFX_CPL_HDR_BUF_RC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_cpl_hdr_buf_rc : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_CPL_HDR_BUF_RC;

/* Define the union U_IB_ODR_DFX_PCPL_SBM_RC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_pcpl_sbm_rc : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PCPL_SBM_RC;

/* Define the union U_IB_ODR_DFX_AER_PRT_PL_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_aer_rpt_ep_pl_0 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_AER_PRT_PL_0;

/* Define the union U_IB_ODR_DFX_AER_RPT_PL_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_aer_rpt_ep_pl_1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_AER_RPT_PL_1;

/* Define the union U_IB_ODR_SRAM_ECC_STS_CLR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_21               : 31  ; /* [31:1] */
        unsigned int    dfx_sram_ecc_sts_clr : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SRAM_ECC_STS_CLR;

/* Define the union U_IB_ODR_SRAM_ECC_STS_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_sram_ecc_sts_pcplq_sbm : 16  ; /* [31:16] */
        unsigned int    dfx_sram_ecc_sts_npq_sbm   : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SRAM_ECC_STS_0;

/* Define the union U_IB_ODR_SRAM_ECC_STS_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_sram_ecc_sts_npq_attr_buf : 16  ; /* [31:16] */
        unsigned int    dfx_sram_ecc_sts_npq_addr_buf : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SRAM_ECC_STS_1;

/* Define the union U_IB_ODR_SRAM_ECC_STS_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dfx_sram_ecc_sts_pq_attr_buf : 16  ; /* [31:16] */
        unsigned int    dfx_sram_ecc_sts_pq_addr_buf : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SRAM_ECC_STS_2;

/* Define the union U_IB_ODR_SRAM_ECC_STS_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_22                     : 16  ; /* [31:16] */
        unsigned int    dfx_sram_ecc_cplq_attr_buf : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_SRAM_ECC_STS_3;

/* Define the union U_IB_ODR_DFX_QUEUE_DISP_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_queue_disp_cnt : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_QUEUE_DISP_CNT;

/* Define the union U_IB_ODR_DFX_GEN_CPL_CNT_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_gen_cpl_cnt : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_GEN_CPL_CNT_0;

/* Define the union U_IB_ODR_DFX_GEN_CPL_CNT_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_23                  : 8  ; /* [31:24] */
        unsigned int    cfg_dfx_gen_cpl_ur_cnt  : 8  ; /* [23:16] */
        unsigned int    cfg_dfx_gen_cpl_ca_cnt  : 8  ; /* [15:8] */
        unsigned int    cfg_dfx_gen_cpl_err_cnt : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_GEN_CPL_CNT_1;

/* Define the union U_IB_ODR_DFX_NPQ_ARB_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_npq_to_odr_cnt  : 16  ; /* [31:16] */
        unsigned int    cfg_dfx_npq_to_axim_cnt : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_NPQ_ARB_CNT;

/* Define the union U_IB_ODR_DFX_AER_RPT_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_aer_rpt_p_ur_cnt  : 8  ; /* [31:24] */
        unsigned int    cfg_dfx_aer_rpt_p_ca_cnt  : 8  ; /* [23:16] */
        unsigned int    cfg_dfx_aer_rpt_np_ur_cnt : 8  ; /* [15:8] */
        unsigned int    cfg_dfx_aer_rpt_np_ca_cnt : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_AER_RPT_CNT;

/* Define the union U_IB_ODR_DFX_PCPL_SBM_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_pcpl_sbm_cnt : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PCPL_SBM_CNT;

/* Define the union U_IB_ODR_DFX_MSI_HIT_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_24                 : 16  ; /* [31:16] */
        unsigned int    cfg_dfx_ib_msi_hit_cnt : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_MSI_HIT_CNT;

/* Define the union U_IB_ODR_DFX_PCPL_SEND_CNT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_pcpl_send_cnt : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_PCPL_SEND_CNT;

/* Define the union U_IB_ODR_DFX_NPQ_SBM_STAT_CLR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_25                     : 31  ; /* [31:1] */
        unsigned int    cfg_dfx_npq_sbm_stat_clear : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_NPQ_SBM_STAT_CLR;

/* Define the union U_IB_ODR_DFX_NPQ_GEN_CPL_BW_0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_26                      : 16  ; /* [31:16] */
        unsigned int    cfg_dfx_npq_gen_cpl_bw_curr : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_NPQ_GEN_CPL_BW_0;

/* Define the union U_IB_ODR_DFX_NPQ_GEN_CPL_BW_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_dfx_npq_gen_cpl_bw_max : 16  ; /* [31:16] */
        unsigned int    cfg_dfx_npq_gen_cpl_bw_ava : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_NPQ_GEN_CPL_BW_1;

/* Define the union U_IB_ODR_DFX_NPQ_SBM_STATE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_27                : 15  ; /* [31:17] */
        unsigned int    cfg_dfx_npq_sbm_state : 17  ; /* [16:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_DFX_NPQ_SBM_STATE;

/* Define the union U_IB_ODR_CNT_CLR_CE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_28     : 30  ; /* [31:2] */
        unsigned int    snap_en    : 1  ; /* [1] */
        unsigned int    cnt_clr_ce : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_CNT_CLR_CE;

/* Define the union U_IB_ODR_INT_SRC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_29                           : 2  ; /* [31:30] */
        unsigned int    int_src_ib_err_tlp_receive       : 1  ; /* [29] */
        unsigned int    int_src_axi_err_bresp_receive    : 1  ; /* [28] */
        unsigned int    int_src_axi_poison_rdata_receive : 1  ; /* [27] */
        unsigned int    int_src_axi_err_rresp_receive    : 1  ; /* [26] */
        unsigned int    int_src_cplq_poison_receive      : 1  ; /* [25] */
        unsigned int    int_src_cplq_hed_err_receive     : 1  ; /* [24] */
        unsigned int    int_src_cplq_data_err_receive    : 1  ; /* [23] */
        unsigned int    int_src_cplq_len_err_receive     : 1  ; /* [22] */
        unsigned int    int_src_pq_poison_receive        : 1  ; /* [21] */
        unsigned int    int_src_pq_hed_err_receive       : 1  ; /* [20] */
        unsigned int    int_src_pq_data_err_receive      : 1  ; /* [19] */
        unsigned int    int_src_pq_len_err_receive       : 1  ; /* [18] */
        unsigned int    int_src_npq_poison_receive       : 1  ; /* [17] */
        unsigned int    int_src_npq_hed_err_receive      : 1  ; /* [16] */
        unsigned int    int_src_npq_data_err_receive     : 1  ; /* [15] */
        unsigned int    int_src_npq_len_err_receive      : 1  ; /* [14] */
        unsigned int    int_src_cplq_attr_buf_ecc_mulbit : 1  ; /* [13] */
        unsigned int    int_src_cplq_attr_buf_ecc_onebit : 1  ; /* [12] */
        unsigned int    int_src_pq_attr_buf_ecc_mulbit   : 1  ; /* [11] */
        unsigned int    int_src_pq_attr_buf_ecc_onebit   : 1  ; /* [10] */
        unsigned int    int_src_pq_addr_buf_ecc_mulbit   : 1  ; /* [9] */
        unsigned int    int_src_pq_addr_buf_ecc_onebit   : 1  ; /* [8] */
        unsigned int    int_src_npq_attr_buf_ecc_mulbit  : 1  ; /* [7] */
        unsigned int    int_src_npq_attr_buf_ecc_onebit  : 1  ; /* [6] */
        unsigned int    int_src_npq_addr_buf_ecc_mulbit  : 1  ; /* [5] */
        unsigned int    int_src_npq_addr_buf_ecc_onebit  : 1  ; /* [4] */
        unsigned int    int_src_pcplq_sbm_ecc_mulbit     : 1  ; /* [3] */
        unsigned int    int_src_pcplq_sbm_ecc_onebit     : 1  ; /* [2] */
        unsigned int    int_src_npq_sbm_ecc_mulbit       : 1  ; /* [1] */
        unsigned int    int_src_npq_sbm_ecc_onebit       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_INT_SRC;

/* Define the union U_IB_ODR_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ib_odr_int_mask                  : 2  ; /* [31:30] */
        unsigned int    int_msk_ib_err_tlp_receive       : 1  ; /* [29] */
        unsigned int    int_msk_axi_err_bresp_receive    : 1  ; /* [28] */
        unsigned int    int_msk_axi_poison_rdata_receive : 1  ; /* [27] */
        unsigned int    int_msk_axi_err_rresp_receive    : 1  ; /* [26] */
        unsigned int    int_msk_cplq_poison_receive      : 1  ; /* [25] */
        unsigned int    int_msk_cplq_hed_err_receive     : 1  ; /* [24] */
        unsigned int    int_msk_cplq_data_err_receive    : 1  ; /* [23] */
        unsigned int    int_msk_cplq_len_err_receive     : 1  ; /* [22] */
        unsigned int    int_msk_pq_poison_receive        : 1  ; /* [21] */
        unsigned int    int_msk_pq_hed_err_receive       : 1  ; /* [20] */
        unsigned int    int_msk_pq_data_err_receive      : 1  ; /* [19] */
        unsigned int    int_msk_pq_len_err_receive       : 1  ; /* [18] */
        unsigned int    int_msk_npq_poison_receive       : 1  ; /* [17] */
        unsigned int    int_msk_npq_hed_err_receive      : 1  ; /* [16] */
        unsigned int    int_msk_npq_data_err_receive     : 1  ; /* [15] */
        unsigned int    int_msk_npq_len_err_receive      : 1  ; /* [14] */
        unsigned int    int_msk_cplq_attr_buf_ecc_mulbit : 1  ; /* [13] */
        unsigned int    int_msk_cplq_attr_buf_ecc_onebit : 1  ; /* [12] */
        unsigned int    int_msk_pq_attr_buf_ecc_mulbit   : 1  ; /* [11] */
        unsigned int    int_msk_pq_attr_buf_ecc_onebit   : 1  ; /* [10] */
        unsigned int    int_msk_pq_addr_buf_ecc_mulbit   : 1  ; /* [9] */
        unsigned int    int_msk_pq_addr_buf_ecc_onebit   : 1  ; /* [8] */
        unsigned int    int_msk_npq_attr_buf_ecc_mulbit  : 1  ; /* [7] */
        unsigned int    int_msk_npq_attr_buf_ecc_onebit  : 1  ; /* [6] */
        unsigned int    int_msk_npq_addr_buf_ecc_mulbit  : 1  ; /* [5] */
        unsigned int    int_msk_npq_addr_buf_ecc_onebit  : 1  ; /* [4] */
        unsigned int    int_msk_pcplq_sbm_ecc_mulbit     : 1  ; /* [3] */
        unsigned int    int_msk_pcplq_sbm_ecc_onebit     : 1  ; /* [2] */
        unsigned int    int_msk_npq_sbm_ecc_mulbit       : 1  ; /* [1] */
        unsigned int    int_msk_npq_sbm_ecc_onebit       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_INT_MASK;

/* Define the union U_IB_ODR_INT_STS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_30                           : 2  ; /* [31:30] */
        unsigned int    int_sts_ib_err_tlp_receive       : 1  ; /* [29] */
        unsigned int    int_sts_axi_err_bresp_receive    : 1  ; /* [28] */
        unsigned int    int_sts_axi_poison_rdata_receive : 1  ; /* [27] */
        unsigned int    int_sts_axi_err_rresp_receive    : 1  ; /* [26] */
        unsigned int    int_sts_cplq_poison_receive      : 1  ; /* [25] */
        unsigned int    int_sts_cplq_hed_err_receive     : 1  ; /* [24] */
        unsigned int    int_sts_cplq_data_err_receive    : 1  ; /* [23] */
        unsigned int    int_sts_cplq_len_err_receive     : 1  ; /* [22] */
        unsigned int    int_sts_pq_poison_receive        : 1  ; /* [21] */
        unsigned int    int_sts_pq_hed_err_receive       : 1  ; /* [20] */
        unsigned int    int_sts_pq_data_err_receive      : 1  ; /* [19] */
        unsigned int    int_sts_pq_len_err_receive       : 1  ; /* [18] */
        unsigned int    int_sts_npq_poison_receive       : 1  ; /* [17] */
        unsigned int    int_sts_npq_hed_err_receive      : 1  ; /* [16] */
        unsigned int    int_sts_npq_data_err_receive     : 1  ; /* [15] */
        unsigned int    int_sts_npq_len_err_receive      : 1  ; /* [14] */
        unsigned int    int_sts_cplq_attr_buf_ecc_mulbit : 1  ; /* [13] */
        unsigned int    int_sts_cplq_attr_buf_ecc_onebit : 1  ; /* [12] */
        unsigned int    int_sts_pq_attr_buf_ecc_mulbit   : 1  ; /* [11] */
        unsigned int    int_sts_pq_attr_buf_ecc_onebit   : 1  ; /* [10] */
        unsigned int    int_sts_pq_addr_buf_ecc_mulbit   : 1  ; /* [9] */
        unsigned int    int_sts_pq_addr_buf_ecc_onebit   : 1  ; /* [8] */
        unsigned int    int_sts_npq_attr_buf_ecc_mulbit  : 1  ; /* [7] */
        unsigned int    int_sts_npq_attr_buf_ecc_onebit  : 1  ; /* [6] */
        unsigned int    int_sts_npq_addr_buf_ecc_mulbit  : 1  ; /* [5] */
        unsigned int    int_sts_npq_addr_buf_ecc_onebit  : 1  ; /* [4] */
        unsigned int    int_sts_pcplq_sbm_ecc_mulbit     : 1  ; /* [3] */
        unsigned int    int_sts_pcplq_sbm_ecc_onebit     : 1  ; /* [2] */
        unsigned int    int_sts_npq_sbm_ecc_mulbit       : 1  ; /* [1] */
        unsigned int    int_sts_npq_sbm_ecc_onebit       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_IB_ODR_INT_STS;


//==============================================================================
/* Define the global struct */
typedef struct
{
    volatile U_IB_ORDER_QUEUE_MODE            IB_ORDER_QUEUE_MODE[3]            ; /* 0 */
    volatile U_IB_ORDER_PORT_MODE             IB_ORDER_PORT_MODE[3]             ; /* 4 */
    volatile U_IB_ODR_MODE_CFG                IB_ODR_MODE_CFG[3]                ; /* C */
    volatile U_IB_ODR_ERR_INJECT              IB_ODR_ERR_INJECT[3]              ; /* 10 */
    volatile U_IB_ODR_NPQ_CTRL                IB_ODR_NPQ_CTRL[3]                ; /* 14 */
    volatile U_IB_ODR_NPQ_BUF_THRES           IB_ODR_NPQ_BUF_THRES[3]           ; /* 18 */
    volatile U_IB_ODR_AER_RPT_CTRL            IB_ODR_AER_RPT_CTRL[3]            ; /* 1C */
    volatile U_IB_ODR_PQ_MERGE_CFG            IB_ODR_PQ_MERGE_CFG[3]            ; /* 40 */
    volatile U_IB_ODR_SO_CTRL_0               IB_ODR_SO_CTRL_0[3]               ; /* 44 */
    volatile U_IB_ODR_SO_CTRL_1               IB_ODR_SO_CTRL_1[3]               ; /* 48 */
    volatile U_IB_ODR_SO_CTRL_2               IB_ODR_SO_CTRL_2[3]               ; /* 4C */
    volatile U_IB_ODR_SO_CTRL_3               IB_ODR_SO_CTRL_3[3]               ; /* 50 */
    volatile U_IB_ODR_SO_CTRL_4               IB_ODR_SO_CTRL_4[3]               ; /* 54 */
    volatile U_IB_ODR_THRESHOLD               IB_ODR_THRESHOLD[3]               ; /* 58 */
    volatile U_IB_ODR_SBM_THRESHOLD           IB_ODR_SBM_THRESHOLD[3]           ; /* 5C */
    volatile U_IB_ODR_BW_CAL_EN               IB_ODR_BW_CAL_EN[3]               ; /* 70 */
    volatile U_IB_ODR_BW_CAL_CLR              IB_ODR_BW_CAL_CLR[3]              ; /* 74 */
    volatile U_IB_ODR_NPQ_SBM_STAT_CTRL       IB_ODR_NPQ_SBM_STAT_CTRL[3]       ; /* 80 */
    volatile U_IB_ODR_NPQ_SBM_GEN_CPL_MODE    IB_ODR_NPQ_SBM_GEN_CPL_MODE[3]    ; /* 84 */
    volatile U_IB_ODR_DFX_QUEUE_TBL_RD_REQ    IB_ODR_DFX_QUEUE_TBL_RD_REQ[3]    ; /* 100 */
    volatile U_IB_ODR_DFX_QUEUE_TBL_RD_VLD    IB_ODR_DFX_QUEUE_TBL_RD_VLD[3]    ; /* 104 */
    volatile U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_0 IB_ODR_DFX_QUEUE_TBL_RD_DATA_0[3] ; /* 108 */
    volatile U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_1 IB_ODR_DFX_QUEUE_TBL_RD_DATA_1[3] ; /* 10C */
    volatile U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_2 IB_ODR_DFX_QUEUE_TBL_RD_DATA_2[3] ; /* 110 */
    volatile U_IB_ODR_DFX_QUEUE_TBL_RD_DATA_3 IB_ODR_DFX_QUEUE_TBL_RD_DATA_3[3] ; /* 114 */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_REQ      IB_ODR_DFX_HDR_BUF_RD_REQ[3]      ; /* 118 */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_VLD      IB_ODR_DFX_HDR_BUF_RD_VLD[3]      ; /* 11C */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_DATA_0   IB_ODR_DFX_HDR_BUF_RD_DATA_0[3]   ; /* 120 */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_DATA_1   IB_ODR_DFX_HDR_BUF_RD_DATA_1[3]   ; /* 124 */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_DATA_2   IB_ODR_DFX_HDR_BUF_RD_DATA_2[3]   ; /* 128 */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_DATA_3   IB_ODR_DFX_HDR_BUF_RD_DATA_3[3]   ; /* 12C */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_DATA_4   IB_ODR_DFX_HDR_BUF_RD_DATA_4[3]   ; /* 130 */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_DATA_5   IB_ODR_DFX_HDR_BUF_RD_DATA_5[3]   ; /* 134 */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_DATA_6   IB_ODR_DFX_HDR_BUF_RD_DATA_6[3]   ; /* 138 */
    volatile U_IB_ODR_DFX_HDR_BUF_RD_DATA_7   IB_ODR_DFX_HDR_BUF_RD_DATA_7[3]   ; /* 13C */
    volatile U_IB_ODR_DFX_QUEUE_TYPE_RO_SEL   IB_ODR_DFX_QUEUE_TYPE_RO_SEL[3]   ; /* 140 */
    volatile U_IB_ODR_DFX_QUEUE_TBL0_RO_0     IB_ODR_DFX_QUEUE_TBL0_RO_0[3]     ; /* 144 */
    volatile U_IB_ODR_DFX_QUEUE_TBL0_RO_1     IB_ODR_DFX_QUEUE_TBL0_RO_1[3]     ; /* 148 */
    volatile U_IB_ODR_DFX_QUEUE_TBL1_RO_0     IB_ODR_DFX_QUEUE_TBL1_RO_0[3]     ; /* 14C */
    volatile U_IB_ODR_DFX_QUEUE_TBL1_RO_1     IB_ODR_DFX_QUEUE_TBL1_RO_1[3]     ; /* 150 */
    volatile U_IB_ODR_DFX_QUEUE_TBL2_RO_0     IB_ODR_DFX_QUEUE_TBL2_RO_0[3]     ; /* 154 */
    volatile U_IB_ODR_DFX_QUEUE_TBL2_RO_1     IB_ODR_DFX_QUEUE_TBL2_RO_1[3]     ; /* 158 */
    volatile U_IB_ODR_DFX_QUEUE_TBL3_RO_0     IB_ODR_DFX_QUEUE_TBL3_RO_0[3]     ; /* 15C */
    volatile U_IB_ODR_DFX_QUEUE_TBL3_RO_1     IB_ODR_DFX_QUEUE_TBL3_RO_1[3]     ; /* 160 */
    volatile U_IB_ODR_DFX_NP_HDR_BUF_RO       IB_ODR_DFX_NP_HDR_BUF_RO[3]       ; /* 164 */
    volatile U_IB_ODR_DFX_P_HDR_BUF_RO        IB_ODR_DFX_P_HDR_BUF_RO[3]        ; /* 168 */
    volatile U_IB_ODR_DFX_CPL_HDR_BUF_RO      IB_ODR_DFX_CPL_HDR_BUF_RO[3]      ; /* 16C */
    volatile U_IB_ODR_DFX_PCPL_SBM_RO_0       IB_ODR_DFX_PCPL_SBM_RO_0[3]       ; /* 170 */
    volatile U_IB_ODR_DFX_PCPL_SBM_RO_1       IB_ODR_DFX_PCPL_SBM_RO_1[3]       ; /* 174 */
    volatile U_IB_ODR_DFX_PCPL_SEND_RO        IB_ODR_DFX_PCPL_SEND_RO[3]        ; /* 178 */
    volatile U_IB_ODR_DFX_QUEUE_DISP_RO       IB_ODR_DFX_QUEUE_DISP_RO[3]       ; /* 180 */
    volatile U_IB_ODR_PORT_IDLE_STATUS        IB_ODR_PORT_IDLE_STATUS[3]        ; /* 1A0 */
    volatile U_IB_ODR_DFX_PQ_BW_0             IB_ODR_DFX_PQ_BW_0[3]             ; /* 1B0 */
    volatile U_IB_ODR_DFX_PQ_BW_1             IB_ODR_DFX_PQ_BW_1[3]             ; /* 1B4 */
    volatile U_IB_ODR_DFX_PQ_BW_2             IB_ODR_DFX_PQ_BW_2[3]             ; /* 1B8 */
    volatile U_IB_ODR_DFX_PQ_BW_3             IB_ODR_DFX_PQ_BW_3[3]             ; /* 1BC */
    volatile U_IB_ODR_DFX_PQ_BW_4             IB_ODR_DFX_PQ_BW_4[3]             ; /* 1C0 */
    volatile U_IB_ODR_DFX_PQ_BW_5             IB_ODR_DFX_PQ_BW_5[3]             ; /* 1C4 */
    volatile U_IB_ODR_DFX_PQ_BW_6             IB_ODR_DFX_PQ_BW_6[3]             ; /* 1C8 */
    volatile U_IB_ODR_DFX_PQ_BW_7             IB_ODR_DFX_PQ_BW_7[3]             ; /* 1CC */
    volatile U_IB_ODR_DFX_CPLQ_BW_0           IB_ODR_DFX_CPLQ_BW_0[3]           ; /* 1D0 */
    volatile U_IB_ODR_DFX_CPLQ_BW_1           IB_ODR_DFX_CPLQ_BW_1[3]           ; /* 1D4 */
    volatile U_IB_ODR_DFX_CPLQ_BW_2           IB_ODR_DFX_CPLQ_BW_2[3]           ; /* 1D8 */
    volatile U_IB_ODR_DFX_CPLQ_BW_3           IB_ODR_DFX_CPLQ_BW_3[3]           ; /* 1DC */
    volatile U_IB_ODR_DFX_CPLQ_BW_4           IB_ODR_DFX_CPLQ_BW_4[3]           ; /* 1E0 */
    volatile U_IB_ODR_DFX_CPLQ_BW_5           IB_ODR_DFX_CPLQ_BW_5[3]           ; /* 1E4 */
    volatile U_IB_ODR_DFX_CPLQ_BW_6           IB_ODR_DFX_CPLQ_BW_6[3]           ; /* 1E8 */
    volatile U_IB_ODR_DFX_CPLQ_BW_7           IB_ODR_DFX_CPLQ_BW_7[3]           ; /* 1EC */
    volatile U_IB_ODR_DFX_NP_HDR_BUF_RC       IB_ODR_DFX_NP_HDR_BUF_RC[3]       ; /* 200 */
    volatile U_IB_ODR_DFX_P_HDR_BUF_RC        IB_ODR_DFX_P_HDR_BUF_RC[3]        ; /* 204 */
    volatile U_IB_ODR_DFX_CPL_HDR_BUF_RC      IB_ODR_DFX_CPL_HDR_BUF_RC[3]      ; /* 208 */
    volatile U_IB_ODR_DFX_PCPL_SBM_RC         IB_ODR_DFX_PCPL_SBM_RC[3]         ; /* 20C */
    volatile U_IB_ODR_DFX_AER_PRT_PL_0        IB_ODR_DFX_AER_PRT_PL_0[3]        ; /* 210 */
    volatile U_IB_ODR_DFX_AER_RPT_PL_1        IB_ODR_DFX_AER_RPT_PL_1[3]        ; /* 214 */
    volatile U_IB_ODR_SRAM_ECC_STS_CLR        IB_ODR_SRAM_ECC_STS_CLR[3]        ; /* 21C */
    volatile U_IB_ODR_SRAM_ECC_STS_0          IB_ODR_SRAM_ECC_STS_0[3]          ; /* 220 */
    volatile U_IB_ODR_SRAM_ECC_STS_1          IB_ODR_SRAM_ECC_STS_1[3]          ; /* 224 */
    volatile U_IB_ODR_SRAM_ECC_STS_2          IB_ODR_SRAM_ECC_STS_2[3]          ; /* 228 */
    volatile U_IB_ODR_SRAM_ECC_STS_3          IB_ODR_SRAM_ECC_STS_3[3]          ; /* 22C */
    volatile U_IB_ODR_DFX_QUEUE_DISP_CNT      IB_ODR_DFX_QUEUE_DISP_CNT[108]    ; /* 240 */
    volatile U_IB_ODR_DFX_GEN_CPL_CNT_0       IB_ODR_DFX_GEN_CPL_CNT_0[3]       ; /* 2D0 */
    volatile U_IB_ODR_DFX_GEN_CPL_CNT_1       IB_ODR_DFX_GEN_CPL_CNT_1[3]       ; /* 2D4 */
    volatile U_IB_ODR_DFX_NPQ_ARB_CNT         IB_ODR_DFX_NPQ_ARB_CNT[3]         ; /* 2D8 */
    volatile U_IB_ODR_DFX_AER_RPT_CNT         IB_ODR_DFX_AER_RPT_CNT[3]         ; /* 2DC */
    volatile U_IB_ODR_DFX_PCPL_SBM_CNT        IB_ODR_DFX_PCPL_SBM_CNT[12]       ; /* 340 */
    volatile U_IB_ODR_DFX_MSI_HIT_CNT         IB_ODR_DFX_MSI_HIT_CNT[3]         ; /* 360 */
    volatile U_IB_ODR_DFX_PCPL_SEND_CNT       IB_ODR_DFX_PCPL_SEND_CNT[48]      ; /* 380 */
    volatile U_IB_ODR_DFX_NPQ_SBM_STAT_CLR    IB_ODR_DFX_NPQ_SBM_STAT_CLR[3]    ; /* 3C0 */
    volatile U_IB_ODR_DFX_NPQ_GEN_CPL_BW_0    IB_ODR_DFX_NPQ_GEN_CPL_BW_0[3]    ; /* 3C4 */
    volatile U_IB_ODR_DFX_NPQ_GEN_CPL_BW_1    IB_ODR_DFX_NPQ_GEN_CPL_BW_1[3]    ; /* 3C8 */
    volatile U_IB_ODR_DFX_NPQ_SBM_STATE       IB_ODR_DFX_NPQ_SBM_STATE[3]       ; /* 3CC */
    volatile U_IB_ODR_CNT_CLR_CE              IB_ODR_CNT_CLR_CE[3]              ; /* 3D0 */
    volatile U_IB_ODR_INT_SRC                 IB_ODR_INT_SRC[3]                 ; /* 3E0 */
    volatile U_IB_ODR_INT_MASK                IB_ODR_INT_MASK[3]                ; /* 3E4 */
    volatile U_IB_ODR_INT_STS                 IB_ODR_INT_STS[3]                 ; /* 3E8 */

} S_hipciec_ap_iob_rx_odr_reg_REGS_TYPE;

/* Declare the struct pointor of the module hipciec_ap_iob_rx_odr_reg */
extern volatile S_hipciec_ap_iob_rx_odr_reg_REGS_TYPE *gophipciec_ap_iob_rx_odr_regAllReg;

/* Declare the functions that set the member value */
int iSetIB_ORDER_QUEUE_MODE_cfg_ib_order_queue_mode(unsigned int ucfg_ib_order_queue_mode);
int iSetIB_ORDER_PORT_MODE_cfg_ib_port_dispatch_to_queue(unsigned int ucfg_ib_port_dispatch_to_queue);
int iSetIB_ODR_MODE_CFG_cfg_odr_p_bresp_mode(unsigned int ucfg_odr_p_bresp_mode);
int iSetIB_ODR_MODE_CFG_cfg_gen_cpl_mode(unsigned int ucfg_gen_cpl_mode);
int iSetIB_ODR_MODE_CFG_cfg_p_odr_mode(unsigned int ucfg_p_odr_mode);
int iSetIB_ODR_MODE_CFG_cfg_cpl_odr_mode(unsigned int ucfg_cpl_odr_mode);
int iSetIB_ODR_MODE_CFG_cfg_np_odr_mode(unsigned int ucfg_np_odr_mode);
int iSetIB_ODR_ERR_INJECT_cfg_npq_sbm_resp_err_inject(unsigned int ucfg_npq_sbm_resp_err_inject);
int iSetIB_ODR_ERR_INJECT_cfg_npq_sbm_data_err_inject(unsigned int ucfg_npq_sbm_data_err_inject);
int iSetIB_ODR_ERR_INJECT_cfg_npq_sbm_ecc_err_inject(unsigned int ucfg_npq_sbm_ecc_err_inject);
int iSetIB_ODR_ERR_INJECT_cfg_pcpl_sbm_ecc_err_inject(unsigned int ucfg_pcpl_sbm_ecc_err_inject);
int iSetIB_ODR_ERR_INJECT_cfg_np_hdr_addr_sram_ecc_err_inject(unsigned int ucfg_np_hdr_addr_sram_ecc_err_inject);
int iSetIB_ODR_ERR_INJECT_cfg_p_hdr_addr_sram_ecc_err_inject(unsigned int ucfg_p_hdr_addr_sram_ecc_err_inject);
int iSetIB_ODR_ERR_INJECT_cfg_sram_ecc_err_inject_reserved(unsigned int ucfg_sram_ecc_err_inject_reserved);
int iSetIB_ODR_ERR_INJECT_cfg_np_hdr_attr_sram_ecc_err_inject(unsigned int ucfg_np_hdr_attr_sram_ecc_err_inject);
int iSetIB_ODR_ERR_INJECT_cfg_p_hdr_attr_sram_ecc_err_inject(unsigned int ucfg_p_hdr_attr_sram_ecc_err_inject);
int iSetIB_ODR_ERR_INJECT_cfg_cpl_hdr_attr_sram_ecc_err_inject(unsigned int ucfg_cpl_hdr_attr_sram_ecc_err_inject);
int iSetIB_ODR_NPQ_CTRL_cfg_npq_atomic_blk_mode(unsigned int ucfg_npq_atomic_blk_mode);
int iSetIB_ODR_NPQ_CTRL_cfg_npq_sbm_port_arb_mode(unsigned int ucfg_npq_sbm_port_arb_mode);
int iSetIB_ODR_NPQ_CTRL_cfg_npq_resp_err_resp_ur(unsigned int ucfg_npq_resp_err_resp_ur);
int iSetIB_ODR_NPQ_CTRL_cfg_npq_tlb_abort_resp_ur(unsigned int ucfg_npq_tlb_abort_resp_ur);
int iSetIB_ODR_NPQ_CTRL_cfg_gen_cpl_arb_mode(unsigned int ucfg_gen_cpl_arb_mode);
int iSetIB_ODR_NPQ_BUF_THRES_cfg_npq_port14_buf_thres(unsigned int ucfg_npq_port14_buf_thres);
int iSetIB_ODR_NPQ_BUF_THRES_cfg_npq_port12_buf_thres(unsigned int ucfg_npq_port12_buf_thres);
int iSetIB_ODR_NPQ_BUF_THRES_cfg_npq_port10_buf_thres(unsigned int ucfg_npq_port10_buf_thres);
int iSetIB_ODR_NPQ_BUF_THRES_cfg_npq_port8_buf_thres(unsigned int ucfg_npq_port8_buf_thres);
int iSetIB_ODR_NPQ_BUF_THRES_cfg_npq_port6_buf_thres(unsigned int ucfg_npq_port6_buf_thres);
int iSetIB_ODR_NPQ_BUF_THRES_cfg_npq_port4_buf_thres(unsigned int ucfg_npq_port4_buf_thres);
int iSetIB_ODR_NPQ_BUF_THRES_cfg_npq_port2_buf_thres(unsigned int ucfg_npq_port2_buf_thres);
int iSetIB_ODR_NPQ_BUF_THRES_cfg_npq_port0_buf_thres(unsigned int ucfg_npq_port0_buf_thres);
int iSetIB_ODR_AER_RPT_CTRL_cfg_aer_rpt_adv_post(unsigned int ucfg_aer_rpt_adv_post);
int iSetIB_ODR_PQ_MERGE_CFG_cfg_so_interlved_merge_enable(unsigned int ucfg_so_interlved_merge_enable);
int iSetIB_ODR_PQ_MERGE_CFG_cfg_pq_merge_enable(unsigned int ucfg_pq_merge_enable);
int iSetIB_ODR_SO_CTRL_0_cfg_ib_odr_so_set_7(unsigned int ucfg_ib_odr_so_set_7);
int iSetIB_ODR_SO_CTRL_0_cfg_ib_odr_so_set_6(unsigned int ucfg_ib_odr_so_set_6);
int iSetIB_ODR_SO_CTRL_0_cfg_ib_odr_so_set_5(unsigned int ucfg_ib_odr_so_set_5);
int iSetIB_ODR_SO_CTRL_0_cfg_ib_odr_so_set_4(unsigned int ucfg_ib_odr_so_set_4);
int iSetIB_ODR_SO_CTRL_0_cfg_ib_odr_so_set_3(unsigned int ucfg_ib_odr_so_set_3);
int iSetIB_ODR_SO_CTRL_0_cfg_ib_odr_so_set_2(unsigned int ucfg_ib_odr_so_set_2);
int iSetIB_ODR_SO_CTRL_0_cfg_ib_odr_so_set_1(unsigned int ucfg_ib_odr_so_set_1);
int iSetIB_ODR_SO_CTRL_0_cfg_ib_odr_so_set_0(unsigned int ucfg_ib_odr_so_set_0);
int iSetIB_ODR_SO_CTRL_1_cfg_ib_odr_so_ostd_limit_en(unsigned int ucfg_ib_odr_so_ostd_limit_en);
int iSetIB_ODR_SO_CTRL_1_cfg_ib_odr_so_ostd_num(unsigned int ucfg_ib_odr_so_ostd_num);
int iSetIB_ODR_SO_CTRL_2_cfg_ib_odr_hash_key_low(unsigned int ucfg_ib_odr_hash_key_low);
int iSetIB_ODR_SO_CTRL_3_cfg_ib_odr_hash_key_high(unsigned int ucfg_ib_odr_hash_key_high);
int iSetIB_ODR_SO_CTRL_4_cfg_ib_odr_so_set_mode(unsigned int ucfg_ib_odr_so_set_mode);
int iSetIB_ODR_THRESHOLD_cfg_ib_odr_pq_block_threshold(unsigned int ucfg_ib_odr_pq_block_threshold);
int iSetIB_ODR_THRESHOLD_cfg_ib_odr_cplq_block_threshold(unsigned int ucfg_ib_odr_cplq_block_threshold);
int iSetIB_ODR_THRESHOLD_cfg_ib_odr_npq_block_threshold(unsigned int ucfg_ib_odr_npq_block_threshold);
int iSetIB_ODR_SBM_THRESHOLD_cfg_ib_odr_cpl_sbm_free_threshold(unsigned int ucfg_ib_odr_cpl_sbm_free_threshold);
int iSetIB_ODR_SBM_THRESHOLD_cfg_ib_odr_sbm_pfull_clear_threshold(unsigned int ucfg_ib_odr_sbm_pfull_clear_threshold);
int iSetIB_ODR_SBM_THRESHOLD_cfg_ib_odr_sbm_pfull_high_threshold(unsigned int ucfg_ib_odr_sbm_pfull_high_threshold);
int iSetIB_ODR_SBM_THRESHOLD_cfg_ib_odr_sbm_pfull_low_threshold(unsigned int ucfg_ib_odr_sbm_pfull_low_threshold);
int iSetIB_ODR_BW_CAL_EN_dfx_cplq_disp_bw_cal_en(unsigned int udfx_cplq_disp_bw_cal_en);
int iSetIB_ODR_BW_CAL_EN_dfx_pq_disp_bw_cal_en(unsigned int udfx_pq_disp_bw_cal_en);
int iSetIB_ODR_BW_CAL_CLR_dfx_cplq_disp_bw_cal_clr(unsigned int udfx_cplq_disp_bw_cal_clr);
int iSetIB_ODR_BW_CAL_CLR_dfx_pq_disp_bw_cal_clr(unsigned int udfx_pq_disp_bw_cal_clr);
int iSetIB_ODR_NPQ_SBM_STAT_CTRL_cfg_npq_gen_cpl_stat_port(unsigned int ucfg_npq_gen_cpl_stat_port);
int iSetIB_ODR_NPQ_SBM_STAT_CTRL_cfg_npq_gen_cpl_stat_port_sel(unsigned int ucfg_npq_gen_cpl_stat_port_sel);
int iSetIB_ODR_NPQ_SBM_STAT_CTRL_cfg_npq_gen_cpl_stat_en(unsigned int ucfg_npq_gen_cpl_stat_en);
int iSetIB_ODR_NPQ_SBM_GEN_CPL_MODE_cfg_npq_sbm_resp_err_mode(unsigned int ucfg_npq_sbm_resp_err_mode);
int iSetIB_ODR_DFX_QUEUE_TBL_RD_REQ_cfg_dfx_queue_tbl_rd_en(unsigned int ucfg_dfx_queue_tbl_rd_en);
int iSetIB_ODR_DFX_QUEUE_TBL_RD_REQ_cfg_dfx_queue_tbl_rd_idx(unsigned int ucfg_dfx_queue_tbl_rd_idx);
int iSetIB_ODR_DFX_QUEUE_TBL_RD_VLD_cfg_dfx_queue_tbl_rd_vld(unsigned int ucfg_dfx_queue_tbl_rd_vld);
int iSetIB_ODR_DFX_QUEUE_TBL_RD_DATA_0_cfg_dfx_queue_tbl_rd_data_0(unsigned int ucfg_dfx_queue_tbl_rd_data_0);
int iSetIB_ODR_DFX_QUEUE_TBL_RD_DATA_1_cfg_dfx_queue_tbl_rd_data_1(unsigned int ucfg_dfx_queue_tbl_rd_data_1);
int iSetIB_ODR_DFX_QUEUE_TBL_RD_DATA_2_cfg_dfx_queue_tbl_rd_data_2(unsigned int ucfg_dfx_queue_tbl_rd_data_2);
int iSetIB_ODR_DFX_QUEUE_TBL_RD_DATA_3_cfg_dfx_queue_tbl_rd_data_3(unsigned int ucfg_dfx_queue_tbl_rd_data_3);
int iSetIB_ODR_DFX_HDR_BUF_RD_REQ_cfg_dfx_hdr_buf_rd_en(unsigned int ucfg_dfx_hdr_buf_rd_en);
int iSetIB_ODR_DFX_HDR_BUF_RD_REQ_cfg_dfx_hdr_buf_rd_idx(unsigned int ucfg_dfx_hdr_buf_rd_idx);
int iSetIB_ODR_DFX_HDR_BUF_RD_VLD_cfg_dfx_hdr_buf_rd_vld(unsigned int ucfg_dfx_hdr_buf_rd_vld);
int iSetIB_ODR_DFX_HDR_BUF_RD_DATA_0_cfg_dfx_hdr_buf_rd_data_0(unsigned int ucfg_dfx_hdr_buf_rd_data_0);
int iSetIB_ODR_DFX_HDR_BUF_RD_DATA_1_cfg_dfx_hdr_buf_rd_data_1(unsigned int ucfg_dfx_hdr_buf_rd_data_1);
int iSetIB_ODR_DFX_HDR_BUF_RD_DATA_2_cfg_dfx_hdr_buf_rd_data_2(unsigned int ucfg_dfx_hdr_buf_rd_data_2);
int iSetIB_ODR_DFX_HDR_BUF_RD_DATA_3_cfg_dfx_hdr_buf_rd_data_3(unsigned int ucfg_dfx_hdr_buf_rd_data_3);
int iSetIB_ODR_DFX_HDR_BUF_RD_DATA_4_cfg_dfx_hdr_buf_rd_data_4(unsigned int ucfg_dfx_hdr_buf_rd_data_4);
int iSetIB_ODR_DFX_HDR_BUF_RD_DATA_5_cfg_dfx_hdr_buf_rd_data_5(unsigned int ucfg_dfx_hdr_buf_rd_data_5);
int iSetIB_ODR_DFX_HDR_BUF_RD_DATA_6_cfg_dfx_hdr_buf_rd_data_6(unsigned int ucfg_dfx_hdr_buf_rd_data_6);
int iSetIB_ODR_DFX_HDR_BUF_RD_DATA_7_cfg_dfx_hdr_buf_rd_data_7(unsigned int ucfg_dfx_hdr_buf_rd_data_7);
int iSetIB_ODR_DFX_QUEUE_TYPE_RO_SEL_cfg_dfx_queue_tbl_ro_sel(unsigned int ucfg_dfx_queue_tbl_ro_sel);
int iSetIB_ODR_DFX_QUEUE_TBL0_RO_0_cfg_dfx_queue_tbl0_ro_0(unsigned int ucfg_dfx_queue_tbl0_ro_0);
int iSetIB_ODR_DFX_QUEUE_TBL0_RO_1_cfg_dfx_queue_tbl0_ro_1(unsigned int ucfg_dfx_queue_tbl0_ro_1);
int iSetIB_ODR_DFX_QUEUE_TBL1_RO_0_cfg_dfx_queue_tbl1_ro_0(unsigned int ucfg_dfx_queue_tbl1_ro_0);
int iSetIB_ODR_DFX_QUEUE_TBL1_RO_1_cfg_dfx_queue_tbl1_ro_1(unsigned int ucfg_dfx_queue_tbl1_ro_1);
int iSetIB_ODR_DFX_QUEUE_TBL2_RO_0_cfg_dfx_queue_tbl2_ro_0(unsigned int ucfg_dfx_queue_tbl2_ro_0);
int iSetIB_ODR_DFX_QUEUE_TBL2_RO_1_cfg_dfx_queue_tbl2_ro_1(unsigned int ucfg_dfx_queue_tbl2_ro_1);
int iSetIB_ODR_DFX_QUEUE_TBL3_RO_0_cfg_dfx_queue_tbl3_ro_0(unsigned int ucfg_dfx_queue_tbl3_ro_0);
int iSetIB_ODR_DFX_QUEUE_TBL3_RO_1_cfg_dfx_queue_tbl3_ro_1(unsigned int ucfg_dfx_queue_tbl3_ro_1);
int iSetIB_ODR_DFX_NP_HDR_BUF_RO_cfg_dfx_np_hdr_buf_ro(unsigned int ucfg_dfx_np_hdr_buf_ro);
int iSetIB_ODR_DFX_P_HDR_BUF_RO_cfg_dfx_p_hdr_buf_ro(unsigned int ucfg_dfx_p_hdr_buf_ro);
int iSetIB_ODR_DFX_CPL_HDR_BUF_RO_cfg_dfx_cpl_hdr_buf_ro(unsigned int ucfg_dfx_cpl_hdr_buf_ro);
int iSetIB_ODR_DFX_PCPL_SBM_RO_0_cfg_dfx_pcpl_sbm_ro_0(unsigned int ucfg_dfx_pcpl_sbm_ro_0);
int iSetIB_ODR_DFX_PCPL_SBM_RO_1_cfg_dfx_pcpl_sbm_ro_1(unsigned int ucfg_dfx_pcpl_sbm_ro_1);
int iSetIB_ODR_DFX_PCPL_SEND_RO_cfg_dfx_pcpl_send_ro(unsigned int ucfg_dfx_pcpl_send_ro);
int iSetIB_ODR_DFX_QUEUE_DISP_RO_cfg_dfx_queue_disp_ro(unsigned int ucfg_dfx_queue_disp_ro);
int iSetIB_ODR_PORT_IDLE_STATUS_cfg_dfx_odr_port_idle_status(unsigned int ucfg_dfx_odr_port_idle_status);
int iSetIB_ODR_DFX_PQ_BW_0_dfx_pq_disp_max_bw_0(unsigned int udfx_pq_disp_max_bw_0);
int iSetIB_ODR_DFX_PQ_BW_0_dfx_pq_disp_ava_bw_0(unsigned int udfx_pq_disp_ava_bw_0);
int iSetIB_ODR_DFX_PQ_BW_1_dfx_pq_disp_max_bw_1(unsigned int udfx_pq_disp_max_bw_1);
int iSetIB_ODR_DFX_PQ_BW_1_dfx_pq_disp_ava_bw_1(unsigned int udfx_pq_disp_ava_bw_1);
int iSetIB_ODR_DFX_PQ_BW_2_dfx_pq_disp_max_bw_2(unsigned int udfx_pq_disp_max_bw_2);
int iSetIB_ODR_DFX_PQ_BW_2_dfx_pq_disp_ava_bw_2(unsigned int udfx_pq_disp_ava_bw_2);
int iSetIB_ODR_DFX_PQ_BW_3_dfx_pq_disp_max_bw_3(unsigned int udfx_pq_disp_max_bw_3);
int iSetIB_ODR_DFX_PQ_BW_3_dfx_pq_disp_ava_bw_3(unsigned int udfx_pq_disp_ava_bw_3);
int iSetIB_ODR_DFX_PQ_BW_4_dfx_pq_disp_max_bw_4(unsigned int udfx_pq_disp_max_bw_4);
int iSetIB_ODR_DFX_PQ_BW_4_dfx_pq_disp_ava_bw_4(unsigned int udfx_pq_disp_ava_bw_4);
int iSetIB_ODR_DFX_PQ_BW_5_dfx_pq_disp_max_bw_5(unsigned int udfx_pq_disp_max_bw_5);
int iSetIB_ODR_DFX_PQ_BW_5_dfx_pq_disp_ava_bw_5(unsigned int udfx_pq_disp_ava_bw_5);
int iSetIB_ODR_DFX_PQ_BW_6_dfx_pq_disp_max_bw_6(unsigned int udfx_pq_disp_max_bw_6);
int iSetIB_ODR_DFX_PQ_BW_6_dfx_pq_disp_ava_bw_6(unsigned int udfx_pq_disp_ava_bw_6);
int iSetIB_ODR_DFX_PQ_BW_7_dfx_pq_disp_max_bw_7(unsigned int udfx_pq_disp_max_bw_7);
int iSetIB_ODR_DFX_PQ_BW_7_dfx_pq_disp_ava_bw_7(unsigned int udfx_pq_disp_ava_bw_7);
int iSetIB_ODR_DFX_CPLQ_BW_0_dfx_cplq_disp_max_bw_0(unsigned int udfx_cplq_disp_max_bw_0);
int iSetIB_ODR_DFX_CPLQ_BW_0_dfx_cplq_disp_ava_bw_0(unsigned int udfx_cplq_disp_ava_bw_0);
int iSetIB_ODR_DFX_CPLQ_BW_1_dfx_cplq_disp_max_bw_1(unsigned int udfx_cplq_disp_max_bw_1);
int iSetIB_ODR_DFX_CPLQ_BW_1_dfx_cplq_disp_ava_bw_1(unsigned int udfx_cplq_disp_ava_bw_1);
int iSetIB_ODR_DFX_CPLQ_BW_2_dfx_cplq_disp_max_bw_2(unsigned int udfx_cplq_disp_max_bw_2);
int iSetIB_ODR_DFX_CPLQ_BW_2_dfx_cplq_disp_ava_bw_2(unsigned int udfx_cplq_disp_ava_bw_2);
int iSetIB_ODR_DFX_CPLQ_BW_3_dfx_cplq_disp_max_bw_3(unsigned int udfx_cplq_disp_max_bw_3);
int iSetIB_ODR_DFX_CPLQ_BW_3_dfx_cplq_disp_ava_bw_3(unsigned int udfx_cplq_disp_ava_bw_3);
int iSetIB_ODR_DFX_CPLQ_BW_4_dfx_cplq_disp_max_bw_4(unsigned int udfx_cplq_disp_max_bw_4);
int iSetIB_ODR_DFX_CPLQ_BW_4_dfx_cplq_disp_ava_bw_4(unsigned int udfx_cplq_disp_ava_bw_4);
int iSetIB_ODR_DFX_CPLQ_BW_5_dfx_cplq_disp_max_bw_5(unsigned int udfx_cplq_disp_max_bw_5);
int iSetIB_ODR_DFX_CPLQ_BW_5_dfx_cplq_disp_ava_bw_5(unsigned int udfx_cplq_disp_ava_bw_5);
int iSetIB_ODR_DFX_CPLQ_BW_6_dfx_cplq_disp_max_bw_6(unsigned int udfx_cplq_disp_max_bw_6);
int iSetIB_ODR_DFX_CPLQ_BW_6_dfx_cplq_disp_ava_bw_6(unsigned int udfx_cplq_disp_ava_bw_6);
int iSetIB_ODR_DFX_CPLQ_BW_7_dfx_cplq_disp_max_bw_7(unsigned int udfx_cplq_disp_max_bw_7);
int iSetIB_ODR_DFX_CPLQ_BW_7_dfx_cplq_disp_ava_bw_7(unsigned int udfx_cplq_disp_ava_bw_7);
int iSetIB_ODR_DFX_NP_HDR_BUF_RC_cfg_dfx_np_hdr_buf_rc(unsigned int ucfg_dfx_np_hdr_buf_rc);
int iSetIB_ODR_DFX_P_HDR_BUF_RC_cfg_dfx_p_hdr_buf_rc(unsigned int ucfg_dfx_p_hdr_buf_rc);
int iSetIB_ODR_DFX_CPL_HDR_BUF_RC_cfg_dfx_cpl_hdr_buf_rc(unsigned int ucfg_dfx_cpl_hdr_buf_rc);
int iSetIB_ODR_DFX_PCPL_SBM_RC_cfg_dfx_pcpl_sbm_rc(unsigned int ucfg_dfx_pcpl_sbm_rc);
int iSetIB_ODR_DFX_AER_PRT_PL_0_dfx_aer_rpt_ep_pl_0(unsigned int udfx_aer_rpt_ep_pl_0);
int iSetIB_ODR_DFX_AER_RPT_PL_1_dfx_aer_rpt_ep_pl_1(unsigned int udfx_aer_rpt_ep_pl_1);
int iSetIB_ODR_SRAM_ECC_STS_CLR_dfx_sram_ecc_sts_clr(unsigned int udfx_sram_ecc_sts_clr);
int iSetIB_ODR_SRAM_ECC_STS_0_dfx_sram_ecc_sts_pcplq_sbm(unsigned int udfx_sram_ecc_sts_pcplq_sbm);
int iSetIB_ODR_SRAM_ECC_STS_0_dfx_sram_ecc_sts_npq_sbm(unsigned int udfx_sram_ecc_sts_npq_sbm);
int iSetIB_ODR_SRAM_ECC_STS_1_dfx_sram_ecc_sts_npq_attr_buf(unsigned int udfx_sram_ecc_sts_npq_attr_buf);
int iSetIB_ODR_SRAM_ECC_STS_1_dfx_sram_ecc_sts_npq_addr_buf(unsigned int udfx_sram_ecc_sts_npq_addr_buf);
int iSetIB_ODR_SRAM_ECC_STS_2_dfx_sram_ecc_sts_pq_attr_buf(unsigned int udfx_sram_ecc_sts_pq_attr_buf);
int iSetIB_ODR_SRAM_ECC_STS_2_dfx_sram_ecc_sts_pq_addr_buf(unsigned int udfx_sram_ecc_sts_pq_addr_buf);
int iSetIB_ODR_SRAM_ECC_STS_3_dfx_sram_ecc_cplq_attr_buf(unsigned int udfx_sram_ecc_cplq_attr_buf);
int iSetIB_ODR_DFX_QUEUE_DISP_CNT_cfg_dfx_queue_disp_cnt(unsigned int ucfg_dfx_queue_disp_cnt);
int iSetIB_ODR_DFX_GEN_CPL_CNT_0_cfg_dfx_gen_cpl_cnt(unsigned int ucfg_dfx_gen_cpl_cnt);
int iSetIB_ODR_DFX_GEN_CPL_CNT_1_cfg_dfx_gen_cpl_ur_cnt(unsigned int ucfg_dfx_gen_cpl_ur_cnt);
int iSetIB_ODR_DFX_GEN_CPL_CNT_1_cfg_dfx_gen_cpl_ca_cnt(unsigned int ucfg_dfx_gen_cpl_ca_cnt);
int iSetIB_ODR_DFX_GEN_CPL_CNT_1_cfg_dfx_gen_cpl_err_cnt(unsigned int ucfg_dfx_gen_cpl_err_cnt);
int iSetIB_ODR_DFX_NPQ_ARB_CNT_cfg_dfx_npq_to_odr_cnt(unsigned int ucfg_dfx_npq_to_odr_cnt);
int iSetIB_ODR_DFX_NPQ_ARB_CNT_cfg_dfx_npq_to_axim_cnt(unsigned int ucfg_dfx_npq_to_axim_cnt);
int iSetIB_ODR_DFX_AER_RPT_CNT_cfg_dfx_aer_rpt_p_ur_cnt(unsigned int ucfg_dfx_aer_rpt_p_ur_cnt);
int iSetIB_ODR_DFX_AER_RPT_CNT_cfg_dfx_aer_rpt_p_ca_cnt(unsigned int ucfg_dfx_aer_rpt_p_ca_cnt);
int iSetIB_ODR_DFX_AER_RPT_CNT_cfg_dfx_aer_rpt_np_ur_cnt(unsigned int ucfg_dfx_aer_rpt_np_ur_cnt);
int iSetIB_ODR_DFX_AER_RPT_CNT_cfg_dfx_aer_rpt_np_ca_cnt(unsigned int ucfg_dfx_aer_rpt_np_ca_cnt);
int iSetIB_ODR_DFX_PCPL_SBM_CNT_cfg_dfx_pcpl_sbm_cnt(unsigned int ucfg_dfx_pcpl_sbm_cnt);
int iSetIB_ODR_DFX_MSI_HIT_CNT_cfg_dfx_ib_msi_hit_cnt(unsigned int ucfg_dfx_ib_msi_hit_cnt);
int iSetIB_ODR_DFX_PCPL_SEND_CNT_cfg_dfx_pcpl_send_cnt(unsigned int ucfg_dfx_pcpl_send_cnt);
int iSetIB_ODR_DFX_NPQ_SBM_STAT_CLR_cfg_dfx_npq_sbm_stat_clear(unsigned int ucfg_dfx_npq_sbm_stat_clear);
int iSetIB_ODR_DFX_NPQ_GEN_CPL_BW_0_cfg_dfx_npq_gen_cpl_bw_curr(unsigned int ucfg_dfx_npq_gen_cpl_bw_curr);
int iSetIB_ODR_DFX_NPQ_GEN_CPL_BW_1_cfg_dfx_npq_gen_cpl_bw_max(unsigned int ucfg_dfx_npq_gen_cpl_bw_max);
int iSetIB_ODR_DFX_NPQ_GEN_CPL_BW_1_cfg_dfx_npq_gen_cpl_bw_ava(unsigned int ucfg_dfx_npq_gen_cpl_bw_ava);
int iSetIB_ODR_DFX_NPQ_SBM_STATE_cfg_dfx_npq_sbm_state(unsigned int ucfg_dfx_npq_sbm_state);
int iSetIB_ODR_CNT_CLR_CE_snap_en(unsigned int usnap_en);
int iSetIB_ODR_CNT_CLR_CE_cnt_clr_ce(unsigned int ucnt_clr_ce);
int iSetIB_ODR_INT_SRC_int_src_ib_err_tlp_receive(unsigned int uint_src_ib_err_tlp_receive);
int iSetIB_ODR_INT_SRC_int_src_axi_err_bresp_receive(unsigned int uint_src_axi_err_bresp_receive);
int iSetIB_ODR_INT_SRC_int_src_axi_poison_rdata_receive(unsigned int uint_src_axi_poison_rdata_receive);
int iSetIB_ODR_INT_SRC_int_src_axi_err_rresp_receive(unsigned int uint_src_axi_err_rresp_receive);
int iSetIB_ODR_INT_SRC_int_src_cplq_poison_receive(unsigned int uint_src_cplq_poison_receive);
int iSetIB_ODR_INT_SRC_int_src_cplq_hed_err_receive(unsigned int uint_src_cplq_hed_err_receive);
int iSetIB_ODR_INT_SRC_int_src_cplq_data_err_receive(unsigned int uint_src_cplq_data_err_receive);
int iSetIB_ODR_INT_SRC_int_src_cplq_len_err_receive(unsigned int uint_src_cplq_len_err_receive);
int iSetIB_ODR_INT_SRC_int_src_pq_poison_receive(unsigned int uint_src_pq_poison_receive);
int iSetIB_ODR_INT_SRC_int_src_pq_hed_err_receive(unsigned int uint_src_pq_hed_err_receive);
int iSetIB_ODR_INT_SRC_int_src_pq_data_err_receive(unsigned int uint_src_pq_data_err_receive);
int iSetIB_ODR_INT_SRC_int_src_pq_len_err_receive(unsigned int uint_src_pq_len_err_receive);
int iSetIB_ODR_INT_SRC_int_src_npq_poison_receive(unsigned int uint_src_npq_poison_receive);
int iSetIB_ODR_INT_SRC_int_src_npq_hed_err_receive(unsigned int uint_src_npq_hed_err_receive);
int iSetIB_ODR_INT_SRC_int_src_npq_data_err_receive(unsigned int uint_src_npq_data_err_receive);
int iSetIB_ODR_INT_SRC_int_src_npq_len_err_receive(unsigned int uint_src_npq_len_err_receive);
int iSetIB_ODR_INT_SRC_int_src_cplq_attr_buf_ecc_mulbit(unsigned int uint_src_cplq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_SRC_int_src_cplq_attr_buf_ecc_onebit(unsigned int uint_src_cplq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_SRC_int_src_pq_attr_buf_ecc_mulbit(unsigned int uint_src_pq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_SRC_int_src_pq_attr_buf_ecc_onebit(unsigned int uint_src_pq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_SRC_int_src_pq_addr_buf_ecc_mulbit(unsigned int uint_src_pq_addr_buf_ecc_mulbit);
int iSetIB_ODR_INT_SRC_int_src_pq_addr_buf_ecc_onebit(unsigned int uint_src_pq_addr_buf_ecc_onebit);
int iSetIB_ODR_INT_SRC_int_src_npq_attr_buf_ecc_mulbit(unsigned int uint_src_npq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_SRC_int_src_npq_attr_buf_ecc_onebit(unsigned int uint_src_npq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_SRC_int_src_npq_addr_buf_ecc_mulbit(unsigned int uint_src_npq_addr_buf_ecc_mulbit);
int iSetIB_ODR_INT_SRC_int_src_npq_addr_buf_ecc_onebit(unsigned int uint_src_npq_addr_buf_ecc_onebit);
int iSetIB_ODR_INT_SRC_int_src_pcplq_sbm_ecc_mulbit(unsigned int uint_src_pcplq_sbm_ecc_mulbit);
int iSetIB_ODR_INT_SRC_int_src_pcplq_sbm_ecc_onebit(unsigned int uint_src_pcplq_sbm_ecc_onebit);
int iSetIB_ODR_INT_SRC_int_src_npq_sbm_ecc_mulbit(unsigned int uint_src_npq_sbm_ecc_mulbit);
int iSetIB_ODR_INT_SRC_int_src_npq_sbm_ecc_onebit(unsigned int uint_src_npq_sbm_ecc_onebit);
int iSetIB_ODR_INT_MASK_ib_odr_int_mask(unsigned int uib_odr_int_mask);
int iSetIB_ODR_INT_MASK_int_msk_ib_err_tlp_receive(unsigned int uint_msk_ib_err_tlp_receive);
int iSetIB_ODR_INT_MASK_int_msk_axi_err_bresp_receive(unsigned int uint_msk_axi_err_bresp_receive);
int iSetIB_ODR_INT_MASK_int_msk_axi_poison_rdata_receive(unsigned int uint_msk_axi_poison_rdata_receive);
int iSetIB_ODR_INT_MASK_int_msk_axi_err_rresp_receive(unsigned int uint_msk_axi_err_rresp_receive);
int iSetIB_ODR_INT_MASK_int_msk_cplq_poison_receive(unsigned int uint_msk_cplq_poison_receive);
int iSetIB_ODR_INT_MASK_int_msk_cplq_hed_err_receive(unsigned int uint_msk_cplq_hed_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_cplq_data_err_receive(unsigned int uint_msk_cplq_data_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_cplq_len_err_receive(unsigned int uint_msk_cplq_len_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_pq_poison_receive(unsigned int uint_msk_pq_poison_receive);
int iSetIB_ODR_INT_MASK_int_msk_pq_hed_err_receive(unsigned int uint_msk_pq_hed_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_pq_data_err_receive(unsigned int uint_msk_pq_data_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_pq_len_err_receive(unsigned int uint_msk_pq_len_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_npq_poison_receive(unsigned int uint_msk_npq_poison_receive);
int iSetIB_ODR_INT_MASK_int_msk_npq_hed_err_receive(unsigned int uint_msk_npq_hed_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_npq_data_err_receive(unsigned int uint_msk_npq_data_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_npq_len_err_receive(unsigned int uint_msk_npq_len_err_receive);
int iSetIB_ODR_INT_MASK_int_msk_cplq_attr_buf_ecc_mulbit(unsigned int uint_msk_cplq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_MASK_int_msk_cplq_attr_buf_ecc_onebit(unsigned int uint_msk_cplq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_MASK_int_msk_pq_attr_buf_ecc_mulbit(unsigned int uint_msk_pq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_MASK_int_msk_pq_attr_buf_ecc_onebit(unsigned int uint_msk_pq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_MASK_int_msk_pq_addr_buf_ecc_mulbit(unsigned int uint_msk_pq_addr_buf_ecc_mulbit);
int iSetIB_ODR_INT_MASK_int_msk_pq_addr_buf_ecc_onebit(unsigned int uint_msk_pq_addr_buf_ecc_onebit);
int iSetIB_ODR_INT_MASK_int_msk_npq_attr_buf_ecc_mulbit(unsigned int uint_msk_npq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_MASK_int_msk_npq_attr_buf_ecc_onebit(unsigned int uint_msk_npq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_MASK_int_msk_npq_addr_buf_ecc_mulbit(unsigned int uint_msk_npq_addr_buf_ecc_mulbit);
int iSetIB_ODR_INT_MASK_int_msk_npq_addr_buf_ecc_onebit(unsigned int uint_msk_npq_addr_buf_ecc_onebit);
int iSetIB_ODR_INT_MASK_int_msk_pcplq_sbm_ecc_mulbit(unsigned int uint_msk_pcplq_sbm_ecc_mulbit);
int iSetIB_ODR_INT_MASK_int_msk_pcplq_sbm_ecc_onebit(unsigned int uint_msk_pcplq_sbm_ecc_onebit);
int iSetIB_ODR_INT_MASK_int_msk_npq_sbm_ecc_mulbit(unsigned int uint_msk_npq_sbm_ecc_mulbit);
int iSetIB_ODR_INT_MASK_int_msk_npq_sbm_ecc_onebit(unsigned int uint_msk_npq_sbm_ecc_onebit);
int iSetIB_ODR_INT_STS_int_sts_ib_err_tlp_receive(unsigned int uint_sts_ib_err_tlp_receive);
int iSetIB_ODR_INT_STS_int_sts_axi_err_bresp_receive(unsigned int uint_sts_axi_err_bresp_receive);
int iSetIB_ODR_INT_STS_int_sts_axi_poison_rdata_receive(unsigned int uint_sts_axi_poison_rdata_receive);
int iSetIB_ODR_INT_STS_int_sts_axi_err_rresp_receive(unsigned int uint_sts_axi_err_rresp_receive);
int iSetIB_ODR_INT_STS_int_sts_cplq_poison_receive(unsigned int uint_sts_cplq_poison_receive);
int iSetIB_ODR_INT_STS_int_sts_cplq_hed_err_receive(unsigned int uint_sts_cplq_hed_err_receive);
int iSetIB_ODR_INT_STS_int_sts_cplq_data_err_receive(unsigned int uint_sts_cplq_data_err_receive);
int iSetIB_ODR_INT_STS_int_sts_cplq_len_err_receive(unsigned int uint_sts_cplq_len_err_receive);
int iSetIB_ODR_INT_STS_int_sts_pq_poison_receive(unsigned int uint_sts_pq_poison_receive);
int iSetIB_ODR_INT_STS_int_sts_pq_hed_err_receive(unsigned int uint_sts_pq_hed_err_receive);
int iSetIB_ODR_INT_STS_int_sts_pq_data_err_receive(unsigned int uint_sts_pq_data_err_receive);
int iSetIB_ODR_INT_STS_int_sts_pq_len_err_receive(unsigned int uint_sts_pq_len_err_receive);
int iSetIB_ODR_INT_STS_int_sts_npq_poison_receive(unsigned int uint_sts_npq_poison_receive);
int iSetIB_ODR_INT_STS_int_sts_npq_hed_err_receive(unsigned int uint_sts_npq_hed_err_receive);
int iSetIB_ODR_INT_STS_int_sts_npq_data_err_receive(unsigned int uint_sts_npq_data_err_receive);
int iSetIB_ODR_INT_STS_int_sts_npq_len_err_receive(unsigned int uint_sts_npq_len_err_receive);
int iSetIB_ODR_INT_STS_int_sts_cplq_attr_buf_ecc_mulbit(unsigned int uint_sts_cplq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_STS_int_sts_cplq_attr_buf_ecc_onebit(unsigned int uint_sts_cplq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_STS_int_sts_pq_attr_buf_ecc_mulbit(unsigned int uint_sts_pq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_STS_int_sts_pq_attr_buf_ecc_onebit(unsigned int uint_sts_pq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_STS_int_sts_pq_addr_buf_ecc_mulbit(unsigned int uint_sts_pq_addr_buf_ecc_mulbit);
int iSetIB_ODR_INT_STS_int_sts_pq_addr_buf_ecc_onebit(unsigned int uint_sts_pq_addr_buf_ecc_onebit);
int iSetIB_ODR_INT_STS_int_sts_npq_attr_buf_ecc_mulbit(unsigned int uint_sts_npq_attr_buf_ecc_mulbit);
int iSetIB_ODR_INT_STS_int_sts_npq_attr_buf_ecc_onebit(unsigned int uint_sts_npq_attr_buf_ecc_onebit);
int iSetIB_ODR_INT_STS_int_sts_npq_addr_buf_ecc_mulbit(unsigned int uint_sts_npq_addr_buf_ecc_mulbit);
int iSetIB_ODR_INT_STS_int_sts_npq_addr_buf_ecc_onebit(unsigned int uint_sts_npq_addr_buf_ecc_onebit);
int iSetIB_ODR_INT_STS_int_sts_pcplq_sbm_ecc_mulbit(unsigned int uint_sts_pcplq_sbm_ecc_mulbit);
int iSetIB_ODR_INT_STS_int_sts_pcplq_sbm_ecc_onebit(unsigned int uint_sts_pcplq_sbm_ecc_onebit);
int iSetIB_ODR_INT_STS_int_sts_npq_sbm_ecc_mulbit(unsigned int uint_sts_npq_sbm_ecc_mulbit);
int iSetIB_ODR_INT_STS_int_sts_npq_sbm_ecc_onebit(unsigned int uint_sts_npq_sbm_ecc_onebit);

#endif // __HIPCIEC_AP_IOB_RX_ODR_REG_C_UNION_DEFINE_H__
